Field of the Invention
The present invention relates to semiconductor memory devices. More particularly, the present invention relates to a flash memory device and to a method of fabricating a flash memory device.
There is a growing demand for semiconductor memory devices that are more highly integrated, e.g., which have cell areas that are more and more compact. One such semiconductor memory device is a flash memory. A flash memory includes a floating gate disposed over a substrate, a tunnel oxide film interposed between the floating gate and the substrate, a dielectric film stacked on the floating gate, and a control gate disposed on the dielectric film. The most important technical aspect of fabricating highly integrated semiconductor memory devices of this kind is to maintain topological alignment between the various layers constituting the device. In the case of a flash memory cell, pitting may occur in the active region of the cell or malfunctions may occur between adjacent cells if an active region of a cell is not aligned precisely with the floating gate of the cell. Flash memories having self-aligned floating gates have been proposed as a means to obviate such potential problems.
FIGS. 1A through 1E illustrate conventional steps for fabricating a flash memory device.
As shown in FIG. 1A, a pad oxide film 13 and a nitride film 15 are formed on a substrate 11. Subsequently, trenches 16 are formed in the resultant structure using a shallow trench isolation (STI) process.
Next, as shown in FIG. 1B, a high density plasma (HDP) oxide film is formed on the structure. Then, the structure is subjected to a chemical-mechanical polishing process to form field isolation films 21 that isolate active regions from one another.
As shown in FIG. 1C, an etch process is carried out using the pad oxide film 13 as an etch stop layer. As a result, the pad nitride film 15 is removed but the field isolation films 21 and the pad oxide film 13 remain on the substrate 11. In addition, a capping layer 23 is formed over the resultant structure.
Next, as shown in FIG. 1D, an etch process is carried out, using the top surface of the semiconductor substrate 11 as an etch stop, to pattern the field isolation films 21 and remove both the pad oxide film 13 and the capping layer 23. In particular, the upper portions of the field isolation films 21 are patterned so as to each have the shape of a nipple. Then, floating gates 27 are formed as separated from each other by the field isolation films 21.
Finally, as shown in FIG. 1E, upper portions of the field isolation films 21 between the floating gates 27 are etched, and a dielectric film 29 is formed thereon. Subsequently, a polysilicon layer 31 is deposited on the dielectric film 29. The polysilicon layer 31 will be processed to form the control gates.
In fabricating such a structure, if the cell areas were minimized, the pitch between the field isolation films 21 would be reduced and hence, the portions of the dielectric film 29 would adhere to each other as shown in FIG. 2. That is, no spaces would exist for control gates between the respective portions of the dielectric film 29, and only the upper portions of the floating gates would face the control gates. The coupling ratio, which is the ratio between a voltage applied to the control gate and the voltage induced at the floating gate of a flash memory having the structure shown in FIG. 2, is small and thus, is more prone to give rise to program or erasing errors during operation.